Hi,

We have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.

We are even taking care of the case sensitivity.

Our file name, new created project name and entity name in the code are all same.

Any idea?

Please help.
Thanks!

I didn't find the right solution from the Internet.

References https://www.alteraforum.com/forum/showthread.php?t=3857

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